1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device for use in measuring timing of an internal control signal and a measurement circuit for measuring the timing of the internal control signal.
2. Description of Related Art
As miniaturization of a semiconductor manufacturing process has been advanced, serious influences have been brought to circuit operations due to variations of finished semiconductor devices. On designing the semiconductor devices, a timing margin has thus far been confirmed by assuring circuit operations which would be carried out under best conditions in all of terms, such as processes, voltages, temperatures, and under worst conditions in all of the above-mentioned terms.
However, when variations in processes seriously influence circuit operations, the above-mentioned designing method can not guarantee a margin for the circuit operations and makes it difficult to assure required properties.
Under the circumstances, proposal has been offered about a method of mounting, on each chip, a monitor circuit for monitoring a finished state of each device, detecting a monitoring result, and carrying out fine adjustment of, for example, internal voltages, to guarantee an operation margin of each circuit.
However, it has been found out that the above-mentioned method has had problems. One of the problems has been found out such that finished or completed transistors are varied in characteristics not only among product lots and wafers but also among chips of each wafer. Taking this into account, it might be considered that a plurality of monitor circuit are arranged at the sacrifice of a chip size on each chip in consideration of variations of characteristics within each chip. With this structure, it is necessary to allow margins among the respective measurement results of the plurality of the monitor circuits to some extent and to subtly control the internal voltages and so on by fine adjustment. But, such fine adjustment often encounters difficulties and such margins among the respective measurement results are liable to often give superfluous margins.
Herein, description will be made in detail about the method of monitoring the finished devices by the use of such a monitor circuit. As usual, a clock synchronization delay control circuit is incorporated in a semiconductor integrated circuit within a semiconductor device. In this case, the clock synchronization delay control circuit adjusts a delay time within internal circuits of the semiconductor integrated circuit by producing an internal clock signal which is synchronized with an external clock signal and which is delayed by n clock cycles of the external clock signal, where n is an integer.
The clock synchronization delay control circuit is classified into a SAD (Synchronous Adjustable Delay) type and a DLL (Delay Locked Loop) type, both of which use a delay monitor circuit. In order to precisely synchronize the internal clock signal with the external clock signal, the delay monitor circuit should have a delay time which is accurately equal to a sum of a delay time of a clock receiver and a delay time of an output buffer.
Thus, the clock synchronization delay control circuit is used to measure an input delay time tRC of the clock receiver relative to the external clock signal and an output delay time tDR of the output buffer. As a result, the clock synchronization delay control circuit makes it possible to measure the input delay times of the clock receiver and the output buffer, to perform operation in a delay measurement mode with the clock synchronization delay control circuit implemented in the semiconductor integrated circuit, and to set, in the delay monitor circuit, an actual signal delay time of each internal circuit and a delay time of outputting data which depends on a load state of an external data bus. Therefore, it is possible to accurately measure an actual delay time in the semiconductor integrated circuit including the delay monitor circuit.
Alternatively, disclosure is made in JP-A-2000-269423 (Patent Document 1) about a semiconductor integrated circuit which includes an improved clock synchronization delay control circuit. Specifically, the disclosed clock synchronization delay control circuit has a clock receiver which generates an internal clock signal CLK in response to an external clock signal and a synchronization delay control circuit and a delay monitor circuit both of which are given the internal clock signal CLK. In a delay measurement mode, the synchronization delay control circuit has a circuit which produces a pseudo internal clock signal DCLK acting as a signal to be measured. The pseudo internal clock signal DCLK is delayed by a clock driver and an output control circuit and is delivered as the internal clock signal to a data input/output circuit. The data input/output circuit sends a data signal to an external data bus through an output buffer and an output driver and fetches the data signal through a data receiver.
In this case, the delay monitor circuit sets a delay time which is equal to a sum of an output delay time tDR and a delay time tRC. Herein, the output delay time tDR represents a delay time from a generation time of the pseudo internal clock signal DCLK to an output time of the output data signal DOUT output through an external data bus while an input delay time tRC represents a delay time at a data receiver.
With this structure, when the pseudo data signal of “H” level is output to the external data bus, a data signal DAT is delayed by the input delay time tRC at the data receiver and is produced. In this case, a measurement start signal STR is produced in response to the pseudo internal clock signal DCLK while a measurement stop signal STP is produced in response to the data signal DAT. Responsive to the measurement start signal STR and the measurement stop signal STP, the delay monitor circuit can measure the delay time represented by the sum of the output delay time tDR and the input delay time tRC.
In Patent Document 1, it is pointed out that an actual delay time can be accurately measured by the delay monitor circuit when the delay time of the clock receiver is substantially equal to the delay time of the data receiver. In other words, the clock receiver of Patent Document 1 has a structure equivalent with the data receiver.
In addition, the external clock input is replaced by the pseudo data signal output to the external data bus. Under the circumstances, the delay time of the clock receiver can become equal to that of the data receiver.
In the case where designing is carried out on the assumption that the clock receiver and the data receiver have the same delay times and the external clock is replaced by the pseudo data signal in the above-mentioned manner, various problems take place as will be mentioned below. At any rate, it is to be noted that the measurement results obtained by the above-mentioned method do not accurately reflect circuit characteristics in a normal operation.
Specifically, the first problem is that the clock receiver and the data receiver do not always have the same characteristics even within the same chip. This is because variations of characteristics can not be neglected even in a single chip due to variations of manufacturing processes as channels of transistors of the semiconductor device become shorter and shorter and the semiconductor device has a high performance.
Practically, since the clock receiver and the data receiver are arranged in different positions from each other on each chip, they do not have the same characteristics. As a result, a difference of the delay times can not accurately be grasped at every chip in the method mentioned in Patent Document 1.
The second problem is that the external clock bus and the external data bus differ from each other in devices connected to them, in the number of the devices, and in interfaces connected to them and have different response characteristics from each other. This shows that the external clock bus and the external data bus are different from each other in signal waveforms, such as rise/fall waveforms, noise characteristics.
The third problem is that consideration is made in Patent Document 1 only about the delay times of the clock and the data. No consideration is made at all about delay times of any other internal control signals except the clock and the data signals used in the DRAM and the other semiconductor devices.